You can safely assume that your CPU will experience significant changes in the coming decade. As engineers overcome power, heat, and size obstacles, new technology will arrive on your chip. One of the people wielding significant influence over those innovations is Intel CTO, Pat Gelsinger, who gave us this prediction: "By 2010: 30GHz, 10 billion transistors, and a tera-instruction per second." (See our interview with him.)
Now, Intel is not known for timidity when it comes to long-term projections. In fact, the company is over-betting the SIA's (Semiconductor Industry Association) rather conservative 2010 technology roadmap by about 18GHz, but Intel does tend to keep mum about its immediate future roadmaps. AMD, however, leans pretty far the other way, publishing its CPU roadmap right on its Web site. But the company is very close-mouthed about its long-range (currently anything post-eighth generation) technology plans.
 BBUL: Check Your Packaging
The size of your package is no laughing matter. It is an essential, integral structure that feeds power to the chip and draws heat away, transfers information into and out of the mainboard, and protects the chip from possible environmental damage. In Intel's case, its goal of reaching a 30GHz microprocessor sporting 1 billion transistors isn't going to happen without technological innovation in package design. The company is banking on a technology in development called BBUL (bumpless build-up layer). The breakthrough could come with packages that are built up around the silicon die as opposed to manufactured separately and then bonded together.
BBUL isn't the most exciting item on Intel's list, even according to Gelsinger, but it will have an impact on many other innovations currently keeping design engineers awake at night: "I'd call BBUL sort of a meat and potatoes kind of technology; it just makes everything better. It's going to enable greater integration, improved characteristics, and new combinations of technologies coming together, and it's going to be really core to the product line over time."
Package primer. The Pentium 4 and its 55 million transistors is packaged in a flip-chip BGA (Ball Grid Array) package connected to the silicon die by a set of C4 solder bumps. These bumps are the last structures put on and are used to connect the silicon to the package. The package makes an electrical connection between the pins and bumps. Manufacturing of the package begins with the core (middle layer), consisting of a sheet of plastic with copper interconnects, called vias, passing vertically through the core. Holes are laser-drilled and filled with copper so the vias (as many as 10,000 in today's CPUs) can be housed in the core. Copper interconnect layers are then assembled on either side of the core ensuring that each C4 bump is routed to the correct pin. Finally, when all pins are attached, the package is set for insertion into the board. In the P4's BGA case, the pins are replaced by balls that attach to the surface of the board. The limitations of this technology will become obvious as microprocessors increase in complexity requiring that ever more C4 bumps be placed on the shrinking package.
BBUL technology enables higher performing and/or lower power consuming chips to be manufactured. It removes the need for a top interconnect layer by embedding the silicon directly in the package core, rendering the C4 bumps obsolete and making for thinner and lighter packaging. Only a lower interconnect layer is required to be built up. The lack of C4 bumps allows closer connection and improved route signals across different parts of the die. Shorter interconnects reduce inductance. More efficient power performance is possible by capacitors situated on the pin side of the package that are closer to the silicon, allowing it to run at higher speeds. Chips operating at lower voltages will be possible through diminished electrical noise. Reducing power dissipation in tandem with voltage is of prime importance in the quest for eking more MHz from the finite limits of physics.
Intel is hoping its BBUL (bumpless build-up layer) technology, shown here in comparison to the current FCPGA (flip-chip pin grid array) packaging, will help the company reach its 30GHz goal. | Intel is aiming to physically shrink the CPU down in size to little more than the width of a dime with smaller and shorter pins. This will be necessary in the future for smaller form factors such as mini-mobile PCs, cell phones, and PDAs, and most especially when we are all wearing Star Trek communicator pins (more about that in the "Silicon-Based Radio" section). Even more intriguing is that BBUL could allow for multiple chips in the same package. An interconnect layer can make connections from die to pins as well as among the die. Embedding a CPU and chipset into one package is another way to decrease the footprint. Ultimately, the idea is to lay out the CPU, chipset, GPU, memory, and a few other amazing goodies onto a single 1mm-thick substrate.
AMD's resources are not quite as hefty as Intel's 900-strong IC-packaging workforce. But having recently released its first organically based substrate CPU with the Athlon XP, AMD has shifted away from the limitations of ceramic packages. With 0.13-micron and SOI (Silicon-On-Insulator), AMD's eighth-generation Hammer processors will be able to scale better; AMD is playing the packaging game, too. Companies such as NEC and GE have fired blanks in bumpless-bonding chip packaging for military applications, so the nut has yet to be cracked.
Intel still faces some challenges to attain acceptable yields, making the entire process cost effective for mass production. Then, and only then, toward the second half of this decade, will we likely see BBUL-based CPUs in pocket PC-sized devices that transfer data to and from your solar-powered home, your hybrid convertible car, and your Intel-stellar office. Don't worry, though; if desktop PCs still exist, the prospect of playing Quake 9 on a 30GHz BBUL-based CPU will have its own reward. So, how far off is all this? According to Gelsinger, "It's medium term, several years away yet, but I characterize that as on track. The timeline has been laid out . . . and we're still pretty comfortable that the technology is maturing at that rate. Where others have failed with techniques like this, our confidence is building that we truly are going to be able to deliver what was described last year."
Viva la Transistance!
Advances in transistor technology are key, as those little blighters are the silicon-based circuits that process the 1s and 0s on CPUs. The crème de la crème of transistors are currently up at the 1 billion operations per second mark, but the TeraHertz transistor will be much nippier and capable of switching between its "off" and "on" state 1 trillion times per second. But as more high-speed transistors get slapped on to a sliver of silicon, even the most elaborate of cooling techniques won't be enough to cool things down, let alone deal with high-power consumption. (Get in-depth TeraHertz transistor information in the March 2002 issue of CPU.)
This size progression of transistors shows a continuation of the shrinking trend. | At a recent demonstration of the TeraHertz transistor, Gerald Marcyk, Intel's director of components research, said, "Smaller and faster just aren't good enough any more. Power and heat are the biggest issues for this decade. What we are doing with our new transistor structure is helping make devices that are extremely power efficient, concentrating electrical current where it's needed."
Although Intel already possesses chemical vapor deposition tools that can deal with the high k material for use with 300mm wafers, others in the industry are currently moving in the direction of partially depleted SOI. Gelsinger says, "We talked a lot about SOI, but the approach today is a partially depleted substrate, which gets you some benefit but at substantial cost, and the implication of that for mass market approaches is that it's going to be later and more expensive. . . . In contrast, what we have done with the TeraHertz transistor is a locally fully depleted substrate that gives you significant scaling and much greater benefits. So we think that the interim technologies, while there are going to be applications for them, I don't want to imply that there won't be some places where they make sense, I view it more as a sort of a niche technology, but the mainstream isn't going to go that way just because of the cost and manufacturing limitations associated with it. . . . " Though Intel's use of a fully depleted substrate transistor with a "high k gate dielectric" has been demonstrated at 2.6THz, AMD actually has the fastest (currently) .015-micron transistor at 3.3THz. IBM's 2THz silicon germanium (SiGe) technology ("double gate" transistor) is also in the works.
Silicon-Based Radio
Although packaging and transistor cramming are important technologies, a new addition to your future CPU might have the biggest impact on how you compute. It started as a "skunkworks" project involving an Internet tablet concept device containing a display, a wireless connection, and a little bit of computing to tie it all together. What became the CMOS Radio project was initially driven by a couple of engineers who wanted to build on the initial product concept and make it more robust. The problems they saw involved high cost, limited range, and inability to move between different types of wireless networks. Somewhere along the way, they posed the question: Why not use CMOS for the radio?
A smart radio circuit with an automatically reconfigurable wireless network connection is really what they had in mind. In fact, the initial vision was to walk out of Starbucks during an 802.11 session, have the device hand off seamlessly to a cellular network, and ultimately incorporate automatic "sniffing" capability so the device always knows what networks are available and is ready to connect to them automatically. All this within a highly stringent 2X to 3X criteria, meaning that compared to current solutions (think 802.11), the device can't consume more than two to three times the power or cost more than two to three times the price. This is the vision. The reality so far breaks down into two major design problems: the radio transceiver itself, and the controller that enables those nifty multiple protocol connections. But acceptable sniffing performance won't be a stroll in the minimall, either.
In the lab. Steve Pawlowski, director of Communications & Interconnects Technology, one of the engineers mentioned above, and the Intel Fellow who authored the CMOS Radio white paper, was kind enough to give us this status report from inside the research lab where the development platform is emerging. Using high-powered processors, DSP (digital signal processing) techniques, and high-speed digital logic, engineers are constructing a system to be reconfigurable for (currently) 802.11a and an experimental UWB (ultra wide band) prototype application operating in excess of 100Mbps.
This is where marketing goes out the window and the difficult and exhilarating work of technical innovation comes alive: "We are trying new things to compensate for the effects of CMOS as it scales in terms of process and lower voltages so that we can eventually integrate the entire radio subsystem, including power amplifier, low noise amplifier, A/D converters, etc. We want to take the entire radio front end and put it in a piece of silicon in order to get the cost down. So there are some interesting challenges. With some of the other technologies, you can use 2.5- to 3-volt power supplies so you get to take advantage of higher voltage circuits (i.e. a high efficiency Power Amplifier) and better immunity to noise that you don't get with a 1.2- or 1-volt process, if it ever gets to that point. But it's an engineering problem, not really a physics problem that can't be solved." Steve has been bopping around Intel for the last 20 years and has accumulated more than 30 patents along with the hard-earned opportunity to play with such challenging toys, especially if they have the potential to become ubiquitous, play on Intel's core competencies, and can continue to pass muster through regular reviews.
"From the CMOS side, we are in the innovation stage in terms of the circuit development. We have several basic designs and test chips in process. We're characterizing those designs and building the appropriate CAD models so the product group could use those designs, devices, and circuits and apply them to their particular product. The circuits that we build to validate and prototype our designs and technology may not be the circuits that they end up using. So they have access to the circuits we've built, but what we're really developing is the capability and the expertise of the process so they have a library of tools available to go do their product development."
MCA. The truly tricky bit is the reconfigurable MCA (microcoded accelerator) that handles the computations necessary to cope with multiple existing protocols and new ones developed in the future. "Instead of one huge pipeline that tries to do all the computation, we broke down the algorithms into constituent components and then determined the types of computation each one of those components would need. For example, a Viterbi decoder needs different types of computation than a FIR filter. So we broke the protocols up into their constituent elements and we are constructing a pipeline and an ALU (arithmetic-logic unit) for those particular elements. The plan is to make it configurable, to use the same hardware and reconfigure the "control logic" to be able to control that hardware in a different manner." So these constituent elements are connected together in a "hybrid MESH network topology that can be programmed to execute different communications solutions at an energy-per-computation cost less than that of current DSP solutions." Voila! The result is a very flexible math machine capable of conversing in multiple protocols of RF communication that powers up only the necessary areas as needed.
Shown here is a proposed hybrid architecture using the MCA (microcoded accelerator). | "The MCA work is still at what we call the pathfinding stage. We're just getting started in terms of looking at the architecture, how we would interconnect these things, the software, the runtime environment, the development tools, everything. We've been doing work for a while, but it's a longer term project and still early in the discovery stage."
As Gelsinger says, this won't all happen at once: "I very much see incremental changes along the way. CMOS Radio, for example. Today you have cell phones with 60 to 70 odd components in there and three big ICs [integrated circuits]. I definitely see that there is going to be an incremental step . . . where we sweep most if not all that stuff together into the analog chip. That will be one integration, but that's not all the way to the ‘Radio Free Intel' vision of having all that on just a corner of a die."
Although BBUL, TeraHertz transistors, and CMOS radio will all have an impact on the structure and functionality of future CPUs, innovations in photonics, sensor networks, and MEMs (microelectromechanical systems) are also moving toward silicon. What is now considered a CPU may become only a tiny subset of what is on the processor of 2010, and engineers in labs and universities and junior high schools all over the world are just itching to show us the rest.
On The Road Again
30GHz and CMOS Radio can't come soon enough? We've trawled the usual sources to bring you the skinny on this year's anticipated desktop CPU harvest. Intel's Pentium 4 (Northwood) 2.4GHz is the current performance champ. Better performing P4s, with 533MHz FSB speeds (133MHz quadpumped) with the added bonus possibility of PC1066 RDRAM support are set to go live around the time you read this. Intel has already publicly demonstrated a P4 at 3 and 4GHz, so there's life in the ol' P4 yet.
But before gamers jump ship from an AMD Athlon XP to a P4, those 300mm thin wafers packing 0.13-micron Northwoods need some drastic price cuts. Also in Q2, Intel is expected to launch a range of new desktop chipsets supporting 533MHz FSB, integrated graphics, and integrated USB 2.0. For value-minded folks, a new Celeron line with SSE2, the P4's NetBurst architecture, and 400MHz FSB (100MHz quad-pumped) capabilities is expected for summer 2002 with cruising speeds in excess of 1.5GHz. Based on the Willamette core, the new Celeron is expected to have 128KB of L2 cache.
The second half of 2003 will be the start of more exciting things to come with the 0.09-micron-based Prescott featuring more transistors (duh!), HyperThreading (first time on a desktop), and more cache. On the mobile side, Intel currently has the P4-M chip based upon the 0.13-micron Northwood core. The previously top-end Tualatin core used for the PIII-M will eventually be rebadged as a lower-powered, lower-cost, smaller-form-factor mobile Celeron for the rest of the year. However, a new mobile Celeron based upon the Northwood will likely enter the market before the end of 2002. Waiting until next year will open the door to Banias!
AMD keeps chipping away at the market share traditionally dominated by Intel. The company's Athlon XP is still the most compelling CPU on offer in terms of price and performance. Even though the current 0.18-micron Palomino-based Athlon XP 2100+ (clocked at 1.73GHz) can't win in terms of raw MHz, the superior IPC efficiency means that only a P4 2.4GHz pulls ahead in some applications, and AMD CPUs still offer the best overall value. The introduction of the 0.13-micron "Thoroughbred" core is due shortly. The die-size shrink from 0.18-micron should enable higher clock speeds and lower power consumption.
Before the year is out, AMD plans to introduce its first SOI-based 0.13-micron Barton core, which doubles the L2 cache from 256KB to 512KB. AMD will also be introducing its eighth-generation 64-bit Hammer architecture, manufactured on SOI technology. (We covered this in the May 2002 issue of CPU.) And the desktop market may get a dose of SOI 0.13-micron-based ClawHammer this year, as well. On the value side of the fence, the Duron will continue on at higher frequencies, thanks to a new 0.13-micron Appaloosa core, similar to the current Morgan core, but with a 266MHz FSB in the first half of 2002.
Achieving The Dream
So who is actually responsible for reaching the numbers that appear in such predictions as Gelsinger's vision of 2010? Intel's Microprocessor Research Labs (MRL; intel.com/research/mrl) develops key technologies for future microprocessors and platforms ahead of the product development groups. MRL is the leading organization setting the standard for microprocessor development three to 10 years in the future. Dr. Wilfred Pinfold is director of Marketing for MRL; here is how he characterizes his reaction to Gelsinger's prediction of 30GHz, 10 billion transistors, and 1 tera-instruction per second by 2010:
"Well, Pat is an interesting guy because he is both a very good businessman and he's also a very good technical guy, so he comes to those figures from a good understanding of the technology, and I would say that reaching those figures will be a challenge and he knows they will be a challenge."
". . . I look at numbers like this and I say 'Oh, we've really got our work cut out for us', but I do believe it's possible, and I believe the industry will gain an enormous benefit by us managing to stay with those numbers. There's a lot actually underneath those numbers that's not immediately visible. The technology that is required to hit those kinds of performance numbers can be applied not only to the performance vectors but also to the power vectors and to bringing a much wider range of products to [market].
"Not only will the technology that we need to develop over the next eight years (that he is talking about there for 2010) allow us to drive performance on the platform to meet the numbers that he's stating, but it will also allow us to give you laptops that run for multiples of days and systems that can run very cool . . . and microprocessors that will be in small devices that you can have in your pocket [that give] immediate access to the digital world. You can use those technologies in a wide range of ways. So, Pat's given us a real challenge and that's what I'd expect from Pat. We will go and we will meet his challenge." 
by Alex Ross and Joan Wood
Talking Future With Pat Gelsinger, Intel CTO
We caught up with Intel CTO Pat Gelsinger via his mobile phone on Tuesday evening April 9, 2002, 8:00PM as he was catching a plane to Japan. (You'll have to excuse the jet noise.)
CPU: For the record, what CPU specifications do you want to have quoted for the furthest out Intel that is looking?
Gelsinger: The numbers I would cite would be by 2010: 30GHz, 10billion transistors, and 1 tera-instruction per second.
CPU: Do you see incremental stages for integrating the various new technologies we are discussing (BBUL packaging, CMOS Radio, TeraHertz transistor), or will you take your current technology as far as you can and then have an abrupt change?
Gelsinger: I very much see incremental changes along the way. CMOS Radio for example, today you have cell phones 60-70 odd components in there and three big ICs. I definitely see that there is going to be an incremental step and this is the next step where we sweep most if not all that stuff together into the analog chip. That will be one integration, but that's not all the way to the "Radio Free Intel" vision of having all that on just a corner of a die. Now that would be an example of an incremental step that is still several years in the future, yet is only part way to the final vision that we're suggesting. And I see that with sensors, I see that with photonics, each one of those having incremental integrations, steps that are going to allow meaningful progress by the industry toward those end games we described.
CPU: A lot of this development in different areas (BBUL packaging, CMOS Radio, TeraHertz transistors, etc.) is happening in parallel. Is there some sort of hierarchical roadmap in the research department for when you think incremental changes will occur?
Gelsinger: We approach it in two ways. We have carved our research areas up into four major thrusts. One is the core silicon work, second is the core architecture platform work, next is the software layers, and then finally is the networking layer. Within each one of those four areas they have roadmaps of work that extend from two weeks to 10 years. The other thing we are trying to do, and this is where my unique job is, is to try and take a top-down view of that and find a relationship between different areas of research and pull those together into some of these longer-term visions that we are driving toward. Using the CMOS Radio and "Radio Free Intel" example, that combines four different areas of research at Intel. One was the MEMs work, one was the architecture of the CMOS work pulling off analog, another was protocol work for roaming technologies, and another was software work in the area of software-defined radio. Part of my role is to pull those different areas together and then to try to assimilate out of that some of the longer-term views. So both the roadmap for each for those four areas and then a top-down view where we try to tie them together into some more compelling, longer term initiatives.
CPU: As Intel's new CTO, is there a certain amount of influence from your background in Desktop and CPU development that exerts itself?
Gelsinger: Clearly my strong suit is in processors. That's where I spent the majority of my time, really. In the computer side of the house is where my natural technology and experience lies. So an awful lot of what I'm doing these days is getting smart on the communications side of technology. So over Christmas I had one of our optics experts come and spend literally a day giving me "Optics for Dummies." [laughs] So as CTO my job is to crossover the areas of wireless, of optics, of communications, and of computing, as well as the end user view and the network view of those technologies. So while I have good depth personally in the computing area, to do my job and do it well, it's essential that I get smart and build relationships with the key technologists both internally and externally and get those technologists to really compliment the areas that I have as my own natural strengths.
CPU: Compare Intel's "in-house" Method of R&D, partnering with Universities, with AMD's approach of partnering with other companies.
Gelsinger: We partner enormously in our research work. I have lab-lets; I have research programs, joint research work, industry initiatives, joint research collaborations, etc. We drive industry consortiums like EUV. There are just areas of our core business where we chose to make those areas of differentiation. But I'd say that of our areas of research, the mass preponderance of them are done in conjunction with broad swaths of the industry. I point to something like the Intel Developer Forum. We have literally thousands of our customers and competitors alike showing up with the sole purpose of partnering with us in our research, development, and initiative areas.
CPU: Not much has been said recently about the advanced lithography. Any particular reason?
Gelsinger: Our Lithography program is on track, meaning that last year we had a major breakthrough with the EUV technology. We showed it, we demonstrated it, and we're on track to the timeframes that we laid out last year. So it's not that we're not talking about it, just that there's not a whole lot of new news particularly. So the core approach is EUV (Extended UltraViolet) removed from magnification to mirroring technologies to new light sources and the vacuum exposure-everything we talked about last year, we're on track to do it. It's about four or five years away until that becomes product technology.
CPU: How do you rate these technologies in terms of excitement?
Gelsinger: I'd call BBUL sort of a meat and potatoes kind of technology (laughs); it just makes everything better. It's going to enable some greater integration, some improved characteristics, and some new combinations of technologies coming together, and it's going to be really core to the product line over time. But packaging technology just doesn't have that much sex appeal to it [laughs]. I would view the CMOS Radio - "Radio Free Intel" focus as having a tremendous amount of cache associated, and it's also going to be a little bit longer in coming to the point where we've fully accomplished that picture. I think when we get there, not only is it going to have a lot of cache but it's going to be much more significant in opening up new application areas and new usage models that we don't see yet today. So, a little bit further out, a lot of sex appeal, but tremendous impact when we've [roaring jet engine sound] the way to accomplishing that picture.
CPU: Other companies have tried BBUL and not succeeded; how far off are you?
Gelsinger: It's medium term, several years away yet, but I characterize that as on track. The timeline has been laid out. It was a two-year ride, and it was a little bit further than that and we're still pretty comfortable that the technology is maturing at that rate. Where others have failed with techniques like this, our confidence is building that we truly are going to be able to deliver what was described last year.
CPU: How do you compare this to the Silicon-On-Insulator methods?
Gelsinger: We talked a lot about SOI, but the approach today is a partially depleted substrate that gets you some benefit but at substantial cost, and the implication of that for mass-market approaches is that it's going to be later and more expensive, and you can save that in other ways. In contrast, what we have done with the TeraHertz transistor is a locally fully depleted substrate that gives you significant scaling and much greater benefits. So we think that the interim technologies, while there are going to be applications for them, I don't want to imply that there won't be some places where they make sense, I view it more as a sort of a niche technology, but the mainstream isn't going to go that way just because of the cost and manufacturing limitations associated with it. That's why we think the TeraHertz is a new transistor structure with a long-term approach that is more scaleable, much better and has a much greater long-term return. So that's where we put our focus.
CPU: Who/What inspires you most?
Gelsinger: There have been two very substantial influences in my life and my career. One is, of course, Andy Grove. I gave a presentation back in the early 486 days and a few days after that presentation Andy calls me up and starts grilling me on my career plans at Intel. And after talking to me about those for a while, he said, "Those are lousy answers! Be in my office in two weeks with better ones" and that began a mentoring relationship that has transpired. He provided the extra guidance to me. The other one is I became a Christian early in my career, I was somewhat radical and out of control with my own personal life and my relationship with Jesus Christ put me on a very firm personal footing which has really allowed a lot of strength and skills to grow and become fully deployed.
CPU: If there were one thing about computing that you could change, what would it be?
Gelsinger: Well today, (laughs) it would be broadband! If there was some way that we could have a real drive to deliver end-user consumable bandwidth, I think everything that we do would be dramatically changed. I don't care if it's wired or wireless. The lack of a data network imperative at the national level is a travesty and will fundamentally limit the growth of computing.
CPU: What do you consider to be the biggest technological breakthrough in history?
Gelsinger: Maybe this is just a little bit of where you stand, but you have to look at the integrated circuit. Part of the reason I say that is I view silicon as sort of the steel of the last 30 years and it's the steel industry of the next 50 years. It is the fuel, it is the engine behind every piece of innovation associated with computing, with the Internet, and we are barely scratching the surface. And if you look at the entire planet's population, there are 6 billion people, about one-fourth of them have had any impact by the technology we create. I view my job as the CTO of the underlying building block supplier, as touching the other 75%. To put a computing communications device on every desktop and business. Every room of every home and in every pocket of every human being on Earth. As such, I think that we've accomplished a lot but have a huge amount to do over the next three or four decades.
CPU: Are you concerned about monopoly status when you say something like that?
Gelsinger: There's nothing wrong with having very high aspirations, right? We have competition in every piece of our business. That competition helps us to be more aggressive and more creative but our goal is to lead; to be the best supplier in every market that we are in. Literally, with our computing and communications vision, we wanna win 'em all. That's our goal.
CPU: What is the biggest mistake you've ever made?
Gelsinger: The biggest professional mistake [was], I led and launched our video efforts at Intel, the ProShare [video conferencing and Internet communications -Ed] efforts and that ended up being a failure for the company. It relied on high-bandwidth networks, at that time were focused on ISDN, which never became well deployed. It also assumed a "build it and they will come" approach to usage model. We never created a compelling view of an end user value proposition for why they would want video conferencing capabilities. So based on those two things, it was a failure, so I invested a lot of years learning in that failure.
CPU: Do you feel that it is important to have failures because you do learn so much from the pain that they invoke?
Gelsinger: I one hundred and one percent agree. In your success, you don't learn. In your failures you're forced into very deep self-introspective analysis of why and how and what you'd do differently. Successes blind you from learning experiences. Failures force you to do deep learning experiences.
CPU: What's the dumbest thing you ever saw a company do in this industry?
Gelsinger: (Laughs!) This is one you can easily get in trouble with, isn't it? Let me pick one for Intel. That's safer for me to do. . . . We at Intel had many, many of the core Internet innovations sitting in our lab. We never figured out a way to harvest them. Akamai? We did it first; we had it in our own lab. The portal? We had it in our lab. Search engine? We had it in our lab. Web servers? We had it in our labs. We could never figure out what to do with them. [Laughs] Every piece of those businesses could have and should have been Intel's but we just couldn't figure out how to get there.
CPU: Do you think that's a symptom of being so large?
Gelsinger: Part of it is being large. Part of it is being at the wrong level of the industry. When you are a silicon maker, almost a PC-centric silicon maker, everything needs to look like a PC. And we just couldn't key this thing called the Internet. We could never figure out what our Internet strategy was. There were so many of these pieces that we could not quite really put together. The position, the power and influence that we would have today if we had ever figured that out, would really be stunning.
CPU: That "PC-centric" orientation seems to be changing-for the CMOS Radio research, the initial circuit designers are all communications engineers and then the traditional silicon architects are validating what they come up with. Is encouraging this part of your role as CTO?
Gelsinger: That's very much the kind of thing that you kind of hope a CTO will do for you. Whether I'm successful in that, well like anything else, that's yet to be proven. I'm not associated with any particular business unit. And I should be able to uniquely look across these business units and find these relationships and how these things might hook together. And how this hunk of technology going on in this processor group might be appropriate for this communications group and whether I as an individual am successful in that or Intel is successful in having that kind of role, well that's still to be determined. But that is why you would want someone in this kind of capacity because you have the unique purview to look across these different areas of the company and identify these things and also at the same time, be very well networked with the industry so that you can try to develop those relationships to the people who potentially could compliment your technologies and bring them together.
CPU: What's the smartest thing you ever saw a company do in this industry?
Gelsinger: [drops phone, apologizes] Well, sometimes it's hard to separate luck and intelligence. [laughs] But I think Java buy SUN was a brilliant move. They took a random technology that they didn't know what to do with [jet roars overhead] and all of a sudden it became a framework for an entire industry of innovation. They got it at the right time and they ended up positioning it the way. That was just brilliant.
CPU: If you could invent anything, what would it be?
Gelsinger: If I could do one thing? [laughs] These things are always associated with what you are thinking about and doing. [drops phone again] I think there is going to be very fundamental breakthroughs in how people interact, we call this the bigger vision of proactive computing, but it's based on things like these CMOS radios that are going to fundamentally change the way people interact with computers and technology. You are going to be able invent and use them in entirely new ways. I would want to be the guy who invents the killer application for this new "Radio Free" world where we've truly integrated all of these sensors, these cheap radios, these new types of devices and really be the one who creates the architecture, the protocol that really takes that from being an interesting lab project to something that we broadly see implemented in the world.
CPU: Tell us about your "first time" with a computer
Gelsinger: My first experience with a computer. I have sort of a Cinderella career at Intel. I skipped my last year of high school, went and got an associates degree at a tech school. I got involved in electronics and was really interested in electronics and started to work on my associates degree instead of finishing high school, and at that school was the first time I used a computer. We had a training computer, we also had a TRS-80, we also had an RCA 1902, the little 4-bit test bed computer. Those were the first three, and I used them at about the same time, and having touched a computer I became absolutely convinced that that's exactly what I wanted to do with my life. Computers were it. I was sold. And while I had no idea where or how yet and it was well before I even know what Intel was, that was exactly the moment that I realized what I wanted to do.
by Joan Wood
Thank you to Kevin Teixeira. |
Timeline
1971 - Intel introduces the 4004. It has a 4-bit bus and is the first single-chip CPU. The 4004 has 2,300 transistors and runs at 108 to 740KHz. 1972 - Intel's 8008 has an 8-bit bus, 3,500 transistors on 10-microns, and a speed of 800KHz. 1974 - The 8-bit Intel 8080 serves as the brains for the Altair $395 PC Kit. 1975 - AMD introduces the 8080A, a reverse- engineered version of Intel's chip, and gives away a television at the fifth anniversary employee street fair. 1979 - The 8-bit version of the Intel 8088 powers the IBM PC and puts Intel on the map with 5MHz! 1982 - The Intel 80286 is introduced with 134,000 transistors running at 12MHz. Intel also releases the 80186 but not for commercial use. 1985 - Transistors reach 275,000 in the 1.5-micron Intel 386, which runs at 16MHz. It has a 32-bit bus and multi- tasking capabilities. 1989 - The 25MHz 1-micron Intel 486 has 1.2 million transistors. It's the first CPU with a math co-processor. 1991 - The AM386 from AMD has 200,000 transistors. 1992 - Intel's 66MHz486DX2 with 1.2 million transistors is introduced. 1993 - The AMD AM486 reaches 1 million transistors and speeds of 33MHz. The 0.8-micron Intel Pentium has 3.1 million transistors introduced at 66MHz. 1994 - 100MHz is cracked when the Intel Pentium on 0.6-micron arrives. 1995 - 5.5 million transistors appear in the 0.6-micron Pentium Pro, the highest speed to launch at 200MHz. 1996 - AMD introduces the AMD K5. It has 4.3 million transistors and a top speed of 75MHz. 1997 - Intel introduces MMX with the Pentium 200MMX, the Pentium II Klamath (0.35micron), and Deschutes (0.25micron), which cracks 300MHz. AMD's 0.25micron K6 is released at 233MHz 1998 - AMD introduces the K6-2 with 9.3 million transistors. Intel releases the 0.25-micron Celeron 300A (Mendocino), which has 19 million transistors and becomes an overclocker's favorite. 1999 - The AMD K6-3 is released at 0.25. The Intel Pentium III with 9.5 million transistors hits 500MHz and then moves to a 733MHz 0.18-micron Coppermine core with 28 million transistors. AMD's 0.25-micron K7 architecture squeezes the performance delta between the two companies for the first time. 2000 - AMD cracks the 1GHz barrier first with a 0.18-micron K75 core sporting 22 million transistors. Intel strikes back with Pentium III 1GHz. Both companies shift from slot to socket based CPUs. Intel recalls the Pentium III 1.13GHz. 0.18-micron Pentium 4 (Willamette) launches at 1.5GHz with 42 million transistors. The 0.18-micron Athlon (Thunderbird), with 37 million transistors, also approaches the 1.5GHz mark. The AMD value-aimed Duron challenges the Celeron. 2001 - AMD introduces the 0.18-micron Athlon XP (Palomino) with 37.5 million transistors. It lasts into 2002 at 1.73GHz. The Duron breaks 1GHz. Intel releases the first 0.13-micron processors with the Pentium III (Tualatin) and Celeron (Tualatin). Intel breaks 1GHz with Pentium III on the mobile side. The Pentium 4 breaks the 2GHz mark and moves from FC-PGA to micro-BGA package. 2002 - Intel shrinks the P4's die to 0.13-micron with the Northwood (55 million transistors). It reaches speeds of 2.4GHz and moves to a 533MHz FSB. AMD shrinks the Athlon XP die to 0.13-micron with the Thoroughbred core and demonstrates the ClawHammer.
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